3x Acceleration of FPGA and ASIC Development and Validation
The developer’s kit CertifEye is a development, debug, and validation solution. It provides developers with infrastructure that injects known images and videos into FPGA/ASIC processing (IP) or an ISP pipeline under test, process them in FPGAs in near or real time, and return results back to the host.
For validation, the returned data can be viewed, analyzed, or compared with the expected data. CertifEye allows developers to dive right into IP development for FPGA and then thoroughly test and inspect their IPs and is part of the ProcVision Developer’s Suite, which enables software engineers to generate an ISP pipeline on FPGA. ProcVision is a solution for developing, validating, and implementing image processing and pipeline designs on FPGA, allowing users to debug, validate, and run dedicated reliability tests to ensure that results are bit-by-bit accurate. Designs can then either be used in Gidel’s frame grabbers or ported to any Intel FPGA device or other vendor device (FPGA or ASIC) by replacing basic libraries. Changing IP parameters is easy via the ProcWizard debug mode and/or macros, and for complex ISPs, a host program can be written to access and control the ISPs under development. CertifEye can reduce compilation time by half because debugging can take place on a small FPGA and be later compiled for and validated on the target FPGA. IP development companies can use the developer´s kit to easily debug, inspect, validate, demonstrate, and provide evaluation across their IP options, including rapid swapping of different pixel bit widths, numbers of pixels per clock, and even target FPGAs. “CertifEye was initially developed to help a key partner overcome their specific development challenges, but we realized how widely appreciated it would be by the entire developer community,” notes Ofer Pravda, VP Marketing & Sales at Gidel. CertifEye is supported by Gidel’s comprehensive ecosystem of infrastructure and development tools. Clients can now quickly evolve from image processing design to a fully implemented Vision/Imaging system that incorporates grabbing and combined FPGA/host image and vision processing.